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? semiconductor components industries, llc, 2002 april, 2002 rev. 5 1 publication order number: mc10e1652/d mc10e1652 5vecl dual ecl output comparator with latch the mc10e1652 is fabricated using on semiconductor's advanced mosaic iii process and is output compatible with 10h logic devices. in addition, the device is available in both a 16-pin dip and a 20-pin surface mount package. however, the mc10e1652 provides user programmable hysteresis. the latch enable (len a and len b ) input pins operate from standard ecl 10h logic levels. when the latch enable is at a logic high level, the mc10e1652 acts as a comparator; hence, q will be at a logic high level if v1 > v2 (v1 is more positive than v2). q is the complement of q. when the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met. the level of input hysteresis is controlled by applying a bias voltage to the hys pin. the 100 series contains temperature compensation. ? typical 3.0 db bandwidth > 1.0 ghz ? typical v to q propagation delay of 775 ps ? typical output rise/fall of 350 ps ? common mode range 2.0 v to +3.0 v ? individual latch enables ? differential outputs ? operating mode: v cc = 5.0 v, v ee = 5.2 v ? programmable input hysteresis ? no internal input pulldown resistors ? esd protection: > 2 kv hbm, > 100 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 85 devices device package shipping ordering information mc10e1652l cdip16 25 units/rail mc10e1652fn plcc20 46 units/rail mc10e1652fnr2 plcc20 500 units/reel marking diagrams 1 16 a = assembly location wl = wafer lot yy = year ww = work week cdip16 l suffix case 620 mc10e1652l awlyyww plcc20 fn suffix case 775 1651fn awlyyww 1 mc10e 20 http://onsemi.com
mc10e1652 http://onsemi.com 2 pinout: 20-lead plcc (top view) qb gnd nc gnd qa qb len b nc v1b v2b v cc hys nc v ee v cc qa len a nc v2a v1a pinout: 16-pin ceramic dip (top view) 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 hys v cc v2b v1b len b qb qb gnd v ee v cc v1a v2a len a qa qa gnd 19 18 13 17 16 15 14 12 11 10 9 45678 20 1 2 3 warning: all v cc , gnd, and v ee pins must be externally connected to power supply to guarantee proper operation. * all v cc and v cco pins are not tied together on the die. figure 1. logic diagrams and pinout assignments pin description pin function qa, qa ecl differential outputs (a) qb, qb ecl differential outputs (b) lena , lenb ecl latch enable v1a, v1b ecl input comparator 1 v2a, v2b ecl input comparator 2 hys ecl hysteresis control v cc positive supply v ee negative supply nc no connect gnd ground qa qa len a v2a v1a qb qb len b v2b v1b v ee = -5.2 v v cc = +5.0 v hys function table len v1, v2 function h h l v1 > v2 v1 < v2 x h l latched figure 2. logic diagram
mc10e1652 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units vsup total supply voltage |v ee | + |v cc | 12.0 v vpp differential input voltage |v1 v2| 3.7 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 12 12 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. dc characteristics v cc = +5.0 v 5%; v ee = 5.2 v 5% (note 2) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v oh output high voltage (note 3) 1020 840 980 810 920 735 mv v ol output low voltage (note 3) 1950 1630 1950 1630 1950 1600 mv v il input low voltage (len ) 1.95 1.48 1.95 1.48 1.95 1.45 mv v ih input high voltage (len ) 1.17 0.84 1.13 0.81 1.07 0.735 mv ii i ih input current (v1, v2) input high current (len ) 65 150 65 150 65 150 m a i cc i ee positive supply current negative supply current 50 55 50 55 50 55 ma vcmr common mode range (note 4) 2.0 3.0 2.0 3.0 2.0 3.0 v hys hysteresis (note 5) 27 27 30 mv v skew hysteresis skew (note 6) 1.0 1.0 0 mv c in input capacitance dip plcc 3 2 3 2 3 2 pf note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . 3. outputs are terminated through a 50 ohm resistor to gnd2 volts. 4. vcmr min varies 1:1 with v ee ; max varies 1:1 with v cc . 5. the hys pin programming characterization information is shown in figure 2. the hysteresis values indicated in the data sheet are for the condition in which the voltage on the hys pin is set to v ee . 6. hysteresis skew (v skew ) is provided to indicate the offset of the hysteresis window. for example, at 25 c the nominal hysteresis value is 27 mv and the v skew value indicates that the hysteresis was skewed from the reference level by 1 mv in the negative direction. hence the hysteresis window ranged from 14 mv below the reference level to 13 mv above the reference level. all hysteresis measurements w ere determined using a reference voltage of 0 mv. the hysteresis skew values apply over the programming range shown in figure 2.
mc10e1652 http://onsemi.com 4 figure 3. typical hysteresis curve figure 4. hysteresis programming voltage 40 30 20 10 0 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -20 -16 -12 -8 -4 vref 4 8 12 16 20 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 vin, differential input voltage (mv) programming voltage (voltage above vee) q, output voltage (v) hysteresis, (mv) hysteresis t = 0 c t = 85 c t = 25 c ac characteristics v cc = +5.0 v 5%; v ee = 5.2 v 5% (note 7) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd > 1.0 tbd ghz t plh t phl propagation delay to output (note 8) v to q len to q 600 400 750 575 900 750 625 400 775 575 925 750 700 500 850 650 1050 850 ps t s setup time v 450 300 450 300 550 350 ps t h enable hold time v 50 250 50 250 100 250 ps t pw minimum pulse width len 400 400 400 ps t skew within device skew (note 9) 15 15 15 ps t jitter cycletocycle jitter tbd tbd tbd ps t de delay dispersion (ecl levels) (notes 10 11) (notes 10, 12) 100 60 ps t dl delay dispersion (ttl levels) (notes 13, 14) (notes 12, 13) 350 100 ps vpp differential input voltage |v1 v2| 3.7 3.7 3.7 v t r t f rise/fall times (20-80%) 225 325 475 225 325 475 250 375 500 ps 7. input and output parameters vary 1:1 with v cc . 8. the propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the q and q output signals. for propagation delay measurements the threshold level (v thr ) is centered about an 850 mv input logic swing with a slew rate of 0.75 v/ns. there is an insignificant change in the propagation delay over the input common mode range. 9. t skew is the propagation delay skew between comparator a and comparator b for a particular part under identical input conditions. 10. refer to figure 4 and note that the input is at 850 mv ecl levels with the input threshold range between the 20% and 80% points. the del ay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the q and q output signals. 11. the slew rate is 0.25 v/ns for input rising edges. 12. the slew rate is 0.75 v/ns for input rising edges. 13. refer to figure 5 and note that the input is at 2.5 v ttl levels with the input threshold range between the 20% and 80% poin ts. the delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the q and q output signals. 14. the slew rate is 0.3 v/ns for input rising edges.
mc10e1652 http://onsemi.com 5 applications information the timing diagram (figure 5.) is presented to illustrate the mc10e1652's compare and latch features. when the signal on the len pin is at a logic high level, the device is operating in the acompare mode,o and the signal on the input arrives at the output after a nominal propagation delay (t phl , t plh ). the input signal must be asserted for a time, t s , prior to the negative going transition on len and held for a time, t h , after the len transition. after time t h , the latch is operating in the alatch mode,o thus transitions on the input do not appear at the output. the device continues to operate in the alatch modeo until the latch is asserted once again. moreover, the len pulse must meet the minimum pulse width (t pw ) requirement to effect the correct input-output relationship. note that the len waveform in figure 5. shows the len signal swinging around a reference labeled vbb int ; this waveform emphasizes the requirement that len follow typical ecl 10kh logic levels because vbb int is the internally generated reference level, hence is nominally at the ecl vbb level. finally, v od is the input voltage overdrive and represents the voltage level beyond the threshold level (v thr ) to which the input is driven. as an example, if the threshold level is set on one of the comparator inputs as 80 mv and the input signal swing on the complementary input is from zero to 100 mv, the positive going overdrive would be 20 mv and the negative going overdrive would be 80 mv. the result of differing overdrive levels is that the devices have shorter propagation delays with greater overdrive because the threshold level is crossed sooner than the case of lower overdrive levels. typically, semiconductor manufactures refer to the threshold voltage as the input offset voltage (vos) since the threshold voltage is the sum of the externally supplied reference voltage and inherent device offset voltage. figure 5. input/output timing diagram q q v thr v len vbb int v od t pw t h t s t phl t plh(len ) v in
mc10e1652 http://onsemi.com 6 delay dispersion under a constant set of input conditions comparators have a specified nominal propagation delay. however, since propagation delay is a function of input slew rate and input voltage overdrive the delay dispersion parameters, t de and t dt , are provided to allow the user to adjust for these variables (where t de and t dt apply to inputs with standard ecl and ttl levels, respectively). figure 6. and figure 7. define a range of input conditions which incorporate varying input slew rates and input voltage overdrive. for input parameters that adhere to these constraints the propagation delay can be described as: t nom t de (or t dt ) where t nom is the nominal propagation delay. t nom accounts for nonuniformity introduced by temperature and voltage variability, whereas the delay dispersion parameter takes into consideration input slew rate and input voltage overdrive variability. thus a modified propagation delay can be approximated to account for the effects of input conditions that differ from those under which the parts where tested. for example, an application may specify an ecl input with a slew rate of 0.25 v/ns, an overdrive of 17 mv and a temperature of 25 c, the delay dispersion parameter would be 100 ps. the modified propagation delay would be 775 ps 100 ps figure 6. ecl dispersion test input conditions figure 7. ttl dispersion test input conditions 0 v 0.5 v 2.0 v 2.5 v - 1.75 v - 1.58 v - 1.07 v -0.9 v slew rate = 0.75 v/ns slew rate = 0.75 v/ns slew rate = 0.25 v/ns slew rate = 0.30 v/ns input threshold range input threshold range
mc10e1652 http://onsemi.com 7 driver device receiver device q qb d db 50 50 v tt figure 8. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) v tt = gnd 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e1652 http://onsemi.com 8 package dimensions plcc20 fn suffix plastic plcc package case 77502 issue d m n l y brk w v d d s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t x g1 b u z view dd 20 1 s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t c g view s e j r z a 0.004 (0.100) t seating plane s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t h view s k k1 f g1 notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.385 0.395 9.78 10.03 b 0.385 0.395 9.78 10.03 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.350 0.356 8.89 9.04 u 0.350 0.356 8.89 9.04 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.310 0.330 7.88 8.38 k1 0.040 --- 1.02 ---
mc10e1652 http://onsemi.com 9 package dimensions cdip16 l suffix ceramic dip package case 62010 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. a b t f e g n k c seating plane 16 pl d s a m 0.25 (0.010) t 16 pl j s b m 0.25 (0.010) t m l dim min max min max millimeters inches a 0.750 0.785 19.05 19.93 b 0.240 0.295 6.10 7.49 c --- 0.200 --- 5.08 d 0.015 0.020 0.39 0.50 e 0.050 bsc 1.27 bsc f 0.055 0.065 1.40 1.65 g 0.100 bsc 2.54 bsc h 0.008 0.015 0.21 0.38 k 0.125 0.170 3.18 4.31 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 16 9 18
mc10e1652 http://onsemi.com 10 notes
mc10e1652 http://onsemi.com 11 notes
mc10e1652 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e1652/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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